Building Coreboot v3

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Thincan DBE61, DBE62 and DBE63 support is integrated into Coreboot v3 mainline.

DDC pins in VGA connector can be muxed to either TTL-level serial port or DDC port. A TTL-RS232 converter is needed to connect this serial port to computer. If serial port is enabled, the VGA DDC (monitor autodetection) does not work! Artec ships BIOS'es with these pins muxed as DDC pins.

Thincan DBE61 has 256kB BIOS ROM, DBE62 and DBE63 have 512kB BIOS ROM. You can build the image smaller than the ROM size if so large image is not needed. If the image is smaller than the ROM, it MUST BE FLASHED to the top of the ROM (ie padded with zeroes or ones at the beginning)!

Prerequisites

  • Linux PC with working GCC compiler
  • Coreboot v3 release: [[1]]
svn co svn://coreboot.org/repository/coreboot-v3
  • Payload ELF image (pre-built FILO / gPXE(Etherboot) / memtest86 etc).
  • VSA image: [[2]]

Procedure

  1. Download / check out from SVN the coreboot-v3 source code
  2. make menuconfig
    • Mainboard -> Vendor: Artecgroup, Board: DBE61
    • Mainboard -> Rom size: 256kB (DBE61) / 256kB or 512kb (DBE62, DBE63)
    • Console -> log level: Warning
    • Console -> Serial console: enabled for development; disabled for release
    • Payload: set to your payload file name (relative to build root directory)
  3. For release version, disable COM2 to enable VGA DDC:
    • In file mainboard/artecgroup/dbe61/dts set com2_enable to 0
    • In file mainboard/artecgroup/dbe61/stage1.c remove call to cs5536_setup_onchipuart(2)
  4. make
  5. Add VSA to image:
    build/util/lar/lar -C lzma -a build/bios.bin vsa.bin

Now you should have your build/bios.bin file ready.

See also